1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Related Art
In recent years, the advancement of the semiconductor manufacturing technique has promoted the miniaturization of semiconductor devices and the enhancement of the number of devices per unit area of a wafer. For example, in the case of manufacturing memory chips of the same storage capacity, the number of the chips that can be obtained from one silicon wafer can be increased, which can reduce the cost per chip. Also, in the case of manufacturing the memory chips of the same area, the storage capacity per chip can be increased, which enables a larger amount of information to be stored.
There is a case that because of the hyperfine structure, a current density when a transistor is operated and a static leakage current are increased, which results in the increase in the electric power consumption of the semiconductor device. Also, usually, in order to enhance the performance of the semiconductor device, the operational frequency is basically set higher, which consequently increases the electric power consumption.
A technique for suppressing the electric power consumption by decreasing the power voltage and a threshold voltage in response to the advancement of the hyperfine structure is known. However, when the threshold voltage of transistors is decreased correspondingly to the decrease in the power voltage, the off leakage current between the source and the drain of a transistor is increased.
In order to suppress the leakage current, a technique that applies a substrate bias (body bias) is known (for example, refer to Japanese Laid-Open Patent Application (JP-P2004-207749A) and Japanese Patent Publication JP-P3184265). The substrate bias is a weak bias voltage that is applied to the substrate terminal of a Metal Oxide Semiconductor transistor. In the following explanation, a bias in a direction which enhances the flow of the current flowing through the transistor is referred to as the forward substrate bias, and a bias in a direction which suppresses the flow of the current flowing through the transistor is referred to as the reverse substrate bias. In short, when the forward substrate bias is applied to a semiconductor device, the current flowing through the channel of a transistor is enhanced, and the transistor is operated at a higher speed or at a lower voltage. Also, during the period in which a semiconductor device is not operated (typically, when it is referred to as the standby mode or waiting mode), the leakage current can be reduced by applying the reverse substrate bias.
Typically, the semiconductor device includes at least one of a P-channel MOS transistor (hereafter, referred to as a PMOS transistor) and an N-channel MOS transistor (hereafter, referred to as an NMOS transistor). Usually, a PMOS transistor is configured inside an N-well formed on a P-type semiconductor substrate, and the substrate bias for the PMOS transistor (hereafter, referred to as an N-well side substrate bias Vnw) is applied on the N-well. Also, an NMOS transistor is configured inside a P-type semiconductor substrate or P-well, and a substrate bias for the NMOS transistor (hereafter, referred to as a P-well side substrate bias Vpw) is applied on the P-type semiconductor device or P-well.
When the forward substrate bias is applied, a higher potential is applied to the P-type semiconductor constituting the substrate terminal of a MOS transistor, and a lower potential is applied to the N-type semiconductor. In short, with the source potential of each of MOS transistors (which are the NMOS transistors or the PMOS transistors) as a reference potential, by representing the potential difference between the source potential and the substrate potential as the voltage Vbs, the forward substrate bias condition is represented, in the case of the NMOS transistor, by Vbs>0, and in the case of the PMOS transistor, by Vbs<0
In other words, by applying a voltage (hereafter, referred to as the first forward substrate bias Vnw1) which is the forward substrate bias and lower than the power voltage to the N-well constituting the substrate terminal of a PMOS transistor, the current flow in the transistor is enhanced. Also, by applying a voltage (hereafter, referred to as the second forward substrate bias Vpw2) which is the forward substrate bias and higher than the ground voltage to the P-type semiconductor substrate (or P-well) constituting the substrate terminal of an NMOS transistor, the current flow in the transistor is enhanced. Consequently, the operation speed of each of the transistors is enhanced.
On the contrary, when the reverse substrate bias is applied, a lower potential is applied to the P-type semiconductor constituting the substrate terminal of a MOS transistor, and a higher potential is applied to the N-type semiconductor. In short, with the source potential of each of MOS transistors (which are the NMOS transistors or the PMOS transistors) as a reference potential, by representing the potential difference between the source potential and the substrate potential as the voltage Vbs, the reverse substrate bias condition is represented, in the case of the NMOS transistor, by Vbs<0, and in the case of the PMOS transistor, by Vbs>0.
In other words, by applying a voltage (hereafter, referred to as the first reverse substrate bias Vnw2) which is the reverse substrate bias and higher than the power voltage to the N-well constituting the substrate terminal of a PMOS transistor, the leakage current is suppressed. Similarly, by applying a voltage (hereafter, referred to as the second reverse substrate bias Vpw2) which is the reverse substrate bias and lower than the ground voltage to the P-type semiconductor substrate (or P-well) constituting the substrate terminal of the NMOS transistor, the leakage current is suppressed.
On the other hand, in association with the advancement of the hyperfine structure and higher integration of the semiconductor device, the influences of crosstalk and skew caused by coupling capacitance between adjacent signal nets and the like has become unignorable. On this background, in order to reduce the influences of the crosstalk and the skew, a technique using shield wiring is known. In this technique, a signal net crossing to the other signal net and a signal net that is required to be prevented from the crossing from the other signal net exist. By locating a power supply net or ground net on both side of these kinds of signal nets, they are shielded (for example, refer to Japanese Patent Publication JP-P2912184 and Japanese Patent Publication JP-P3293588).
Also, in recent years, various techniques relating to the semiconductor manufacture have been provided, which results in the reduction of the cost for manufacturing semiconductor devices. For example, in a gate array and the like, basic logic circuits (gates) are prepared in advance in the alignment of an array (matrix arrangement) inside the chip, and only the wiring layer is designed and manufactured in accordance with the request of users. Thus, a semiconductor device can be manufactured at a low cost in a short period. Under such technical situations, the significance of the semiconductor device which is firstly designed by a designer and manufactured in accordance with the request of a user is enhanced. By manufacturing the semiconductor device in the method close to an order-made production as mentioned above, the request of a user can be sufficiently satisfied. In such a semiconductor device, the logic circuit which is arranged in array is not usually adopted, and there is a case that required function blocks are irregularly placed.
FIG. 1 is a plan view showing the configuration of a conventional semiconductor chip 101 which is manufactured in the method close to the order-made production and has a function for supplying the above mentioned substrate bias. With reference to FIG. 1, the conventional semiconductor chip 101 is provided with: a clock line 103 for distributing the clock signal generated by a clock driver 102; and shield wirings 107, 108 for reducing the influence of the clock sent through the clock line 103 on the other signal lines. The conventional semiconductor chip 101 is provided with: a Vnw bias node 104 for supplying the N-well side substrate bias Vnw; and a Vpw bias node 105 for supplying the P-well side substrate bias Vpw, and the respective bias nodes 104, 105 are constituted by metal interconnections. Also, as shown in FIG. 1, the Vnw bias node 104 and the Vpw bias node 105 are connected to a substrate bias generating circuit 106.
As mentioned above, in the case of manufacturing a semiconductor device in the method close to the order-made production, the logic circuits are not usually arranged in array, and there is the case that the required function blocks are irregularly arranged. Thus, in order to supply the substrate bias, the respective bias nodes 104, 105 are wired up to desirable regions through the empty regions of the chip, and the substrate bias is applied through a contact 110.
FIG. 2 is a plan view showing the configuration of the semiconductor circuit installed in a part (a region 109 shown in FIG. 1) of the conventional semiconductor chip 101. As shown in FIG. 2, the conventional semiconductor circuit has the N-well formed in the P-type semiconductor substrate and contains the P-diffusion region 126 in the N-well. Also, an N-diffusion region 127 is formed in the P-type semiconductor substrate. In the conventional semiconductor chip 101, the semiconductor circuit including Complementary MOS that is composed of the NMOS transistor inside the N-diffusion region 127 and the PMOS transistor inside the P-diffusion region 126 is formed. As shown in FIG. 2, the transistor having the CMOS has a gate electrode made of a polysilicon 128, and a signal supplied through the clock line 103 is applied to the gate electrode. With reference to FIG. 2, the conventional semiconductor chip 101 was required to reserve the region dedicated to the wiring for the bias nodes 104, 105. In short, in the conventional semiconductor device, the Vnw bias node 104 and the Vpw bias node 105 were constituted by the dedicated metal interconnections different from the chip wirings (for example, the clock line 103, shield wiring 107 and shield wiring 108).
With reference to FIG. 2, an N+ region 118 is formed in the N-well having the PMOS transistor. The N+ region 118 is connected through the contact 110 to the substrate bias supplying node 104. Namely, the substrate bias supplying node 104 applies the N-well side substrate bias Vnw, which is supplied from the substrate bias generating circuit 106, through the N+ region 118 to the N-well. Also similarly, the conventional semiconductor chip 101 is formed in the P-type semiconductor substrate and provided with a P+ region 119. As shown in FIG. 2, the P+ region 119 is connected through the contact 110 to the substrate bias supplying node 105. The substrate bias supplying node 105 is connected to the substrate bias generating circuit 106, similarly to the substrate bias supplying node 104, and applies the P-well side substrate bias Vpw, which is supplied from the substrate bias generating circuit 106, through the P+ region to the P-type semiconductor substrate.